Topic Replies Activity
Welcome to the discuss.systemverilog.io 2 April 26, 2019
SystemVerilog constraints examples 1 May 20, 2019
Splitting and extracting specific modules from VPD or VCD dump 1 May 22, 2019
SystemVerilog string methods 1 May 1, 2019
Convert a hex, int, binary data type to string 1 May 1, 2019
Convert string to int, hex or binary number 1 May 1, 2019
Extracting sub-string from a string 1 May 1, 2019
Comparing strings in SystemVerilog 1 May 1, 2019
UVM field macros
UVM
1 April 30, 2019
SystemVerilog Casting 1 February 24, 2019
SystemVerilog dynamic arrays 1 February 23, 2019
SystemVerilog queues 1 February 23, 2019
SystemVerilog Associative Arrays 1 February 23, 2019
Printing an enum by name 2 February 5, 2019
Declaring an enum 2 February 5, 2019
Creating an enum range 2 February 5, 2019
How to use $countones() 2 January 26, 2019
How to execute shell command from SystemVerilog testbench 2 January 26, 2019
How do I determine the number of address bits needed to address a memory 2 January 26, 2019
How do I print the name of the module 2 January 26, 2019
How do I find out the size of a variable or a struct 2 January 26, 2019
Reading and writing to a file 1 January 24, 2019
`__FILE__ and `__LINE__ 2 June 28, 2018