|
Welcome to the discuss.systemverilog.io
|
|
1
|
1471
|
April 26, 2019
|
|
Signed arithmetic on vectors
|
|
0
|
608
|
December 4, 2021
|
|
eMMC memory structure
|
|
0
|
569
|
November 24, 2021
|
|
SystemVerilog Parametrized Module
|
|
1
|
1775
|
September 14, 2020
|
|
Need to design Verilog code for turing machine on EDAplayground.com
|
|
0
|
1052
|
May 23, 2020
|
|
SystemVerilog constraints examples
|
|
0
|
3829
|
May 20, 2019
|
|
Splitting and extracting specific modules from VPD or VCD dump
|
|
2
|
4598
|
February 6, 2020
|
|
Running regression in modelsim on windows based platform
|
|
1
|
1258
|
August 21, 2019
|
|
SystemVerilog string methods
|
|
0
|
15902
|
May 1, 2019
|
|
Convert a hex, int, binary data type to string
|
|
0
|
7644
|
May 1, 2019
|
|
Convert string to int, hex or binary number
|
|
0
|
16430
|
May 1, 2019
|
|
Extracting sub-string from a string
|
|
0
|
4802
|
May 1, 2019
|
|
Comparing strings in SystemVerilog
|
|
0
|
8658
|
May 1, 2019
|
|
UVM field macros
|
|
0
|
5370
|
April 30, 2019
|
|
SystemVerilog Casting
|
|
0
|
14321
|
February 24, 2019
|
|
SystemVerilog dynamic arrays
|
|
0
|
2230
|
February 23, 2019
|
|
SystemVerilog queues
|
|
0
|
3047
|
February 23, 2019
|
|
SystemVerilog Associative Arrays
|
|
0
|
6504
|
February 23, 2019
|
|
Printing an enum by name
|
|
1
|
2871
|
February 5, 2019
|
|
Declaring an enum
|
|
1
|
1918
|
February 5, 2019
|
|
Creating an enum range
|
|
1
|
2805
|
February 5, 2019
|
|
How to use $countones()
|
|
1
|
23114
|
January 26, 2019
|
|
How to execute shell command from SystemVerilog testbench
|
|
1
|
3529
|
January 26, 2019
|
|
How do I determine the number of address bits needed to address a memory
|
|
1
|
2187
|
January 26, 2019
|
|
How do I print the name of the module
|
|
1
|
2928
|
January 26, 2019
|
|
How do I find out the size of a variable or a struct
|
|
1
|
10687
|
January 26, 2019
|
|
Reading and writing to a file
|
|
0
|
937
|
January 24, 2019
|
|
`__FILE__ and `__LINE__
|
|
1
|
4763
|
June 28, 2018
|
