Topics related to SystemVerilog language and LRM
Discussion about this site, its organization, how it works, and how we can improve it.
Topics related to UVM
All things related to Formal Verification
General verification topics. Can also include questions on chip/lab bringup and testing.
Topics related to anything design – including ASIC/FPGA design, board design, etc.
Topics related to tools from vendors such as Synopsys, Cadence and Mentor Graphics