Category Topics

Tools

Topics related to tools from vendors such as Synopsys, Cadence and Mentor Graphics
2

SystemVerilog

Topics related to SystemVerilog language and LRM
20

UVM

Topics related to UVM
1

Site Feedback

Discussion about this site, its organization, how it works, and how we can improve it.
1
0

Formal

All things related to Formal Verification
0

Verification

General verification topics. Can also include questions on chip/lab bringup and testing.
0

Design

Topics related to anything design – including ASIC/FPGA design, board design, etc.
0