SystemVerilog

Topics related to SystemVerilog language and LRM

Site Feedback

Discussion about this site, its organization, how it works, and how we can improve it.

UVM

Topics related to UVM

Formal

All things related to Formal Verification

Verification

General verification topics. Can also include questions on chip/lab bringup and testing.

Design

Topics related to anything design – including ASIC/FPGA design, board design, etc.

Tools

Topics related to tools from vendors such as Synopsys, Cadence and Mentor Graphics