Comparing strings in SystemVerilog


#1

There are 3 ways to compare strings

equality : s1 == s2
compare : s1.compare(s2)
icompare: s1.icompare(s2)


  1. Simple equality ==
string s1 = "orange";
string s2 = "orAnge";

// 1 is printed if strings are identical
// 0 is printed if strings mismatch
$display( "Return value = %0d", (s1 == s2));

Output:
Return value = 0

  1. C-style strcmp using string method compare()
// Just like in C
// Return value = 0 then it indicates s1 is equal to s2
// Return value < 0 then it indicates s1 is less than s2
// Return value > 0 then it indicates s2 is less than s1

$display("Return value = %0d", s1.compare(s2));

Output:
Return value = 32

  1. Case insensitive compare using icompare()
// Return value is similar to C strcmp function
$display("Return value = %0d", s1.icompare(s2));

Output:
Return value = 0