Creating an enum range


#1

Is there an easy way to create an enum range? I want something like this, but it is tedious to declare a long list of such an enum

enum {
  REG0, REG1, REG2, REG3
} regname_e;

#2

Absolutely!

SystemVerilog has a rarely used feature that can totally do this. Here’s how you would use it:

enum { REG[0:3]} regname_e;

Few more examples from the LRM

// Creates enums: 
// add=10, sub0=11, sub1=12, sub13, jmp6, jmp7, jump8 
typedef enum { add=10, sub[3], jmp[6:8] } E1;

// Creates enums:
// register0=1, register1=2, register2=10, register3=11, register4=12
enum { register[2] = 1, register[2:4] = 10 } vr;

Here’s a working example that you can test:

module test_enum;
    typedef enum {
        REG[0:7]
    } regname_e;

    initial begin
        regname_e regname;

        regname = REG1;
        $display("regname is %s", regname.name());

        regname = REG5;
        $display("regname is %s", regname.name());
    end
endmodule 

Output

regname is REG1
regname is REG5

Declaring an enum