Signed arithmetic on vectors

Hi all,

Has anyone else had problems with performing signed multiplication with SystemVerilog’s built in * operator on 2D arrays in for loops? When performed like this, the results in Modelsim are incorrect:

wire signed [INPUTS-1:0][DEPTH-1:0] i_values;

localparam PRODUCT_DEPTH = DEPTH * 2;
wire signed [INPUTS-1:0][PRODUCT_DEPTH+1:0] o_products;

genvar i;
generate 
for (i = 0; i < INPUTS; i = i + 1) begin
o_products[i] = i_values[i] * i_values[i];
end
endgenerate

However, when the values are cast as signed explicitly, the simulation is correct:

wire signed [INPUTS-1:0][DEPTH-1:0] i_values;

localparam PRODUCT_DEPTH = DEPTH * 2;
wire signed [INPUTS-1:0][PRODUCT_DEPTH+1:0] o_products;

genvar i;
generate 
for (i = 0; i < INPUTS; i = i + 1) begin
o_products[i] = signed'(i_values[i]) * signed'(i_values[i]);
end
endgenerate

Has anyone else encountered this problem?