Welcome to the discuss.systemverilog.io


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Welcome to Discuss, the systemverilog.io forum.

While the main website is suitable for long form articles, we felt there was a need for a more adequate place for the SystemVerilog community to quickly share and discuss specific topics. In that sense, Discuss is a companion to the main systemverilog.io website.

There are three ways to use Discuss:

  1. Ask your questions to the community
  2. Help answer questions
  3. Share your knowledge on a specific topic. This can be anything from summarizing a general concept in chip design and hardware engineering – to specific quirks that you have discovered with the tools you are using, such as Synopsys VCS or Mentor Questa.

Examples:

  1. This is an example where a specific question about SystemVerilog enums is asked. Post your answers below by leaving a comment, and the original poster (OP) can check-mark which solution worked for them.
  2. Here’s an example where I’ve summarized how SystemVerilog Dynamic Arrays can be used. Now, if anyone has a specific question about Dynamic Arrays, or if they can add more information to it – they can simply leave a comment underneath this topic. This way all discussions related to Dynamic Arrays will be contained in one space.

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